This invention pertains generally to the field of lock detectors for receivers of phase shift keyed (PSK) signals used in high frequency electronic data communication systems, and more particularly, to lock detectors utilized in demodulators of quadriphase shift keyed (QPSK) signals.
Phase shift keyed systems have been widely used for high frequency transmission of binary data signals, partly because of their advantages in terms of bandwidth and power efficiency for data transmission. In the ordinary binary phase shift keyed (BPSK) system, a carrier wave at frequency f.sub.0 is modulated by a signal u(t) which is a function of time t, representing a stream of binary data, where u(t)=+1 for a bit value 1, and u(t)=-1 for a bit value 0. The resulting modulated signal amplitude is given by the expression: EQU S(t)=(2P).sup.1/2 u(t)sin(.omega..sub.0 t), (1)
where .omega..sub.0 =2.pi.f.sub.0 is the carrier frequency in radians per second, and P is the transmitted power.
The quadriphase shift keyed (QPSK) system is an improvement over the BPSK system in terms of bandwidth and power efficiency. In the QPSK system two independent data streams are transmitted over the same carrier wave. We can represent these data signals by u.sub.I (t) and u.sub.Q (t) where I and Q stand for "inphase" and "quadriphase" signal channels, and u.sub.I and u.sub.Q take values of either +1 or -1. The modulated signal amplitude is then given by the expression: EQU S(t)=(P/2).sup.1/2 [u.sub.I (t)sin(.omega..sub.0 t)+u.sub.Q (t)cos(.omega..sub.0 t)] (2)
The QPSK transmission scheme described by this expression is a balanced QPSK, in that both the inphase and quadriphase channels have equal amplitude and hence equal power. In cases where the data rate in one channel is lower than in the other channel, it is desirable to attenuate the signal in the channel having a lower data rate. This will provide more power in the channel having a higher data rate, and result in an overall improved bit error rate (BER) for the combined signal. In the unbalanced QPSK (UPQSK) scheme, the modulated signal amplitude is given by the expression:
S(t)=(P/2).sup.1/2 [bu.sub.I (t)sin(.omega..sub.0 t)+au.sub.Q (t)cos(.omega..sub.0 t)] (3)
where a/b is the ratio of the signal in the Q channel to that in the I channel, and a.sup.2 +b.sup.2 =1. Thus, if the Q channel is attenuated relative to the I channel, then a&lt;b.
Receivers of BPSK and QPSK signals commonly employ coherent detection as the most efficient method of recovering the binary data contained in these signals. These receivers include a local voltage-controlled oscillator (VCO) that generates a reference signal that is coherently combined with the input signal. The VCO is swept in frequency until the reference signal becomes locked in phase with the input signal. This phase locking is detected by a "lock detector" circuit. After phase lock, the lock detector generates a DC voltage that is greater than a threshold voltage, and deactivates the sweep signal to the VCO. Typically the lock detector combined with the local oscillator and control circuits form a phase locked loop (PLL).
Lock detector circuits for BPSK demodulators are known in the art. An example of such a circuit is described in U.S. Pat. No. 4,713,630 (Matthews), which discloses a PLL lock detector in a "Costas-type" demodulator circuit. Another example is shown in U.S. Pat. No. 4,860,321 (von der Embse), which describes a demodulator that uses baseband digital signal processing and determines lock conditions by means of certain digital algorithms.
A lock detector for a QPSK demodulator is described in U.S. Pat. No. 4,092,606 (Ryan), and comprises a PLL that drives a voltage controlled oscillator (VCO) coupled to the two data channels. This demodulator also includes a dithering circuit connected to the VCO that produces a tracking error of approximately 2 degrees in the phase locking. This error causes degradation of the BER. The Ryan circuit is suitable only for a balanced QPSK signal, i.e. for a ratio a/b near unity. The BER degradation is even larger if this circuit is used for UQPSK signals.
U.S. Pat. No. 4,870,382 (Keate et al.) also discloses a lock detector circuit for QPSK signals, in which absolute value detectors are used instead of analog multipliers to increase the speed of the detector. This scheme is advantageous only for signal-to-noise ratios that are large. Furthermore, this circuit is also suitable only for balanced QPSK signals.
In short, the previous demodulator lock detecting circuits have been designed and are useful only for QPSK signals that are balanced. No previous system is known for lock detection in demodulators of UQPSK signals.